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CPU design
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11	Design of Parallel and High Performance Computing HS 2013 Markus P¨ uschel, Torsten Hoefler Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-10-10 09:58:44 Cache coherency MESI protocol Cache coherence Cache False sharing Draft:Cache memory CPU cache
12	Comparative analysis between QuickThread and Intel® Threading Building Blocks (TBB) Copyright © 2009 QuickThread Programming, LLC www.quickthreadprogramming.com Add to Reading List Source URL: www.quickthreadprogramming.com Language: English - Date: 2012-05-03 14:20:38 Parallel computing Concurrent computing Application programming interfaces Software design patterns Central processing unit Threading Building Blocks Thread OpenMP Monitor CPU cache C++11 Multithreading
13	Accurate emulation of CPU performance Tomasz Buchert1 Lucas Nussbaum2 1 Add to Reading List Source URL: www.loria.fr Language: English - Date: 2011-10-12 09:35:39 Central processing unit Computing Engineering Computer performance Emulator Processor design CPU time
14	ATHENA III PC/104 Single Board Computer Intel Atom E640T CPU and Integrated Autocalibrating Data Acquisition Highly integrated Intel Atom E-Series SBC 2-in-1 design (CPU + DAQ) reduces size and cost, increases ruggedness Add to Reading List Source URL: www.qbm.es Language: English - Date: 2013-06-28 06:22:54
15	Summary of Track-Finder Test-Beam Experience Add to Reading List Source URL: www.phys.ufl.edu Language: English - Date: 2003-10-07 13:08:31 Oscillators Electronic design Phase-locked loop CPU multiplier Clock rate Electronic engineering Clock signal Electronics
16	Summary of Track-Finder Test-Beam Experience Add to Reading List Source URL: www.phys.ufl.edu Language: English - Date: 2003-10-16 07:57:13 Oscillators Electronic design Phase-locked loop CPU multiplier Clock rate Electronic engineering Clock signal Electronics
17	The Design and Implementation of Open vSwitch Ben Pfaff, Justin Pettit, Teemu Koponen, Ethan Jackson, Andy Zhou, Jarno Rajahalme, Jesse Gross, Alex Wang, Joe Stringer, and Pravin Shelar, VMware, Inc.; Keith Amidon, Awake Add to Reading List Source URL: www.usenix.org Language: English Computer networking CPU cache Hash table Packet Processing NetBSD Routing table Lookup table Traffic flow Computing Routing OpenFlow
18	Microsoft PowerPoint - 2 UoB NMI_LowPowerVerificationFINAL Add to Reading List Source URL: www.cs.bris.ac.uk Language: English - Date: 2014-03-11 07:15:43 Digital electronics Computer architecture Program optimization CPU design Instruction set Pin Power optimization Electronic engineering Central processing unit Electronic design automation
19	EN164: Design of Computing Systems Lecture 25: Memory Systems 1 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:57 Memory hierarchy Cache Dynamic random-access memory CAS latency Random-access memory Locality of reference CPU cache Computer memory Computer hardware Computing
20	EN164: Design of Computing Systems Lecture 31: Memory Systems 7 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:57 Computer memory Computer architecture Computing Translation lookaside buffer CPU cache Page table Page Memory management unit Cache Computer hardware Virtual memory Central processing unit

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